1. Field of the Invention
The present invention relates to an output buffer having a pair of MOS transistors provided at a final stage.
2. Description of the Background Art
FIG. 44 is a circuit diagram showing an example of constitution of input and output circuits of a conventional semiconductor integrated circuit device with a signal level converting function.
A semiconductor integrated circuit with a signal level converting function is a semiconductor integrated circuit device having a function of converting the level of signal voltage supplied from a device operating by a supply voltage in the LSI, and outputting to an external circuit operating by a supply voltage different from the supply voltage of the circuit (internal circuit) in the LSI, and a function of converting the signal supplied by an external device of different supply voltage system into a signal level of an internal circuit, and transmitting inside.
To an input and output terminal 1, an internal circuit is connected through an input buffer 10. Through an output buffer circuit 9, the input and output terminal 1 is also connected with a control terminal 2 for receiving a control signal IN1 from the internal circuit, and an input terminal 3 for receiving an output signal IN2 from the internal circuit.
The output buffer circuit 9 comprises an input and output control circuit 6, a signal level converting circuit 7, and a buffer circuit 8a, and the control terminal 2 and input terminal 3 are connected to the input and output control circuit 6. The input and output control circuit 6 sends an output to the signal level converting circuit 7, and the signal level converting circuit 7 sends an output to the buffer circuit 8a through connection points N13, N23.
In the input and output control circuit 6 and a front half of the signal level converting circuit 7, a first supply potential VDD1 and a grounding potential GND which determine a supply voltage of the internal circuit, are applied to put them into action. On the other hand, in a rear half of the signal level converting circuit 7 and the buffer circuit 8a, a second supply potential VDD2 higher than the first supply potential VDD1 and grounding potential GND are applied to put them in action. The second supply potential VDD2 and grounding potential GND are supplied respectively from a supply potential point 4 and a grounding potential point 5.
When the control signal IN1 is at H level, the connection points N13 and N14 are respectively L level (grounding potential) and H level (second supply potential VDD2) by means of the signal level converting circuit 7, whether the output signal IN2 is at L level or H level. Consequently, both transistors Q9a and Q10 of the buffer circuit 8a are turned off, and the buffer circuit 8a comes in high impedance state relative to the input and output terminal 1. As a result, the signal from the outside given to the input and output terminal 1 is transmitted to the input buffer 10 without damage.
On the other hand, when the control signal IN1 is at L level, provided the output signal IN2 is at L level, the connection points N13 and N14 are both at L level by means of the signal level converting circuit 7. Consequently, the transistors Q9a and Q10 of the buffer circuit 8a are respectively turned off and on, so that L level is issued to the input and output terminal 1.
When the control signal IN1 is at L level and output signal IN2 is at H level, the connection points N13 and N14 are both at H level by means of the signal level converting circuit 7. Consequently, the transistors Q9a and Q10 of the buffer circuit 8a are respectively turned on and off, so that H level is issued to the input and output terminal 1.
FIG. 45 is a circuit diagram showing other example of constitution of input and output circuit of a conventional semiconductor integrated circuit device with signal level converting circuit. The constitution in FIG. 45 is similar to that in FIG. 44, except that the buffer circuit 8a is replaced by a buffer circuit 8b. In the buffer circuit 8b, inverter gate G18 and NMOS transistor Q9a in the buffer circuit 8a are replaced by a PMOS transistor Q9b.
In such constitution, too, it is evident that the operation as explained in relation to FIG. 44 is effected.
The conventional semiconductor integrated circuit devices with signal level converting function are thus constituted, and as far as the operation is normal, the set of potentials of the connection points N13 and N23 is any one of (H level and H level), (L level and L level), and (L level and H level).
However, when the first supply potential VDD1 is not applied in the initial state when the second supply potential VDD2 is turned on, the values of the parts of the signal level converting circuit 7 are not determined uniquely. For example, the set of potentials of the connection points N13 and N23 may be (H level and L level). Such status may give rise to a situation of turning on simultaneously the pair of transistors Q9a and Q10 (or Q9b and Q10), and hence flow of unnecessary current (penetration current) between the supply potential point 4 and grounding potential point 5 in the buffer circuit 8a (or 8b).
FIG. 46 is a schematic sectional view of structure of transistors Q9a, Q10 of the buffer circuit 8a. Both transistors Q9a and Q10 are of NMOS type, and are formed in P well provided with grounding potential GND.
Usually, in the NMOS transistor connected between a high potential and a low potential, the wiring is connected so that the potential of the well being formed (hereinafter called well potential) is at low potential.
However, when the well potential of the transistor Q9a is at the grounding potential GND, in the case the transistor Q9a is turned on, the potential of the source S climbs up, and a bias voltage is applied between the source S and well W.
In the absence of the bias voltage, in the case of the transistor Q9a of E (Enhancement) type, when the well potential is set to the grounding potential GND, the second supply potential VDD2 (V) is applied to the gate electrode G, and the second supply potential VDD2 (V) is applied to the drain D, the potential of the source S (input and output terminal 1) is (VDD2-VTN) (V), where VTN is the threshold voltage of the NMOS transistor Q9.
When the bias voltage is applied, on the other hand, the VTN is shifted to the positive direction to be VTN' (VTN'&gt;VTN), and the drain current decreases. Therefore, the potential of the input and output terminal 1 becomes (VDD2-VTN') (V), and hence the output potential of H level is lower than that without the bias voltage.
FIG. 47 is a schematic sectional view showing the structure of transistors Q9b, Q10 of the buffer circuit 8b. The transistors Q9b and Q10 are respectively of PMOS type and NMOS type. Hence, the transistor Q9b is formed in the n-well provided with the second supply potential VDD2, and the well potential is set at the second supply potential VDD2. Hence, the problem caused in the transistor Q9a is avoided.